1. Field of the Invention
The present invention generally relates to integrated circuits (ICs). More particularly, the present invention relates to interconnect structures, including multilevel interconnect structures fabricated by damascene methods in which the via contact resistance must be low. The present invention describes various methods and tooling for making improved interconnect structures based on copper damascene wiring having a reduced via contact resistance and stable resistance both during IC operation and reliability stress of the IC device.
2. Description of the Prior Art
Generally, semiconductor devices include a plurality of circuits, which form an integrated circuit fabricated on a silicon single crystal substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires the formation of multi-level or multi-layered interconnection schemes, such as, dual damascene wiring structures based on copper. Copper based interconnects are desirable due to their efficacy in providing high speed signal transmission between large numbers of transistors on a complex semiconductor chip.
Within the interconnection structure, metal vias run perpendicular to the silicon substrate and metal lines run parallel to the silicon substrate. Further enhancement of the speed of signals and reduction of interaction of signals in adjacent copper lines (known as “cross-talk) is achieved in new IC product chips by surrounding the copper lines and vias in a low k or ultralow k dielectric.
Presently, interconnect structures formed on an integrated circuit chip includes at least about 2 to 10 wiring levels fabricated at a minimum lithographic feature size designated about 1× (referred to as “thinwires”) and above these levels are about 2 to 4 wiring levels fabricated at a larger size (referred to as “fatwires”). In one class of prior art structures, the thinwires are formed in a low dielectric constant (k) material having a dielectric constant between about 2 and about 3.5.
However, fabrication problems are associated with these prior art structures. For example, the via contact resistance is high in prior structures due to contamination at the via to line interface. Contamination primarily includes oxygen and/or carbon and is in the form of copper oxide (Cu Oxide) or a carbon based residue (polymeric or amorphous carbon). The carbon residue commonly contains H or F and other undesired elements may be present at the via to line interface.
Another problem associated with these prior art structures is poor adhesion at the via contact, which leads to increased via resistance after the structure is cycled in temperature or after long periods of field operation. The extreme case of increased via resistance is an open via with no contact to the line below, a fatal IC failure mode. Poor adhesion is also due to the same contamination described above.
A further problem during interconnect fabrication is that the shapes and dimensions of the etched via and trench openings are correct after etch, but the shapes and dimensions are distorted, enlarged, degraded or roughened during via cleaning. This problem is most acute when low modulus ultralow k (ULK) dielectrics (k<about 2.7) are used and the via cleaning includes Ar+ bombardment. The Ar+ ions enlarge the via dimensions and erode the bottom of the trenches and even cause roughening of the trench bottom. Pores in the ULK dielectric make this problem severe.